technical data KK24LC04B/08b 4k/8k 2.5v cmos serial eeproms description kk 24lc04b/08b is a 4k-or 8k-bit electrically erasable prom. the device is organized as two or four blocks of 256 x 8 bit m e m o ry with a two wire serial interface. low voltage design perm its operation down to 2.5 volts with standby and act i v e current s of onl y 5 a an d 1 m a resp ectiv ely. th e kk 24lc04b/08b also has a page-write capability for up to 16 by t e s of dat a . the kk 24lc04b/08b is available in the standard 8-pin dip. package t a = -40 ... +85 c pinning n a m e f u n c t i o n v s s g r o u n d sda serial address/data i/o s c l s e r i a l c l o c k w p w r i t e prot ect input vc c +2.5v t o 5.5v power suppl y ao, a1, a2 no internal connection features ? single supply with operation down to 2.5v ? low power cmos technology - 1 m a active current ty pical - 10 a standby current ty pical at 5.5v - 5 a standby current ty pical at 3.0v ? organized as two or four blocks of 256 by tes (2x256x8) and (4x256x8) ? two wire serial interface bus, i 2 c com p atible ? schm itt trigger, filtered inputs for noise suppression ? output slope control to elim inate ground bounce ? 100 khz (2.5v) and 400 khz (5v) com p atibility ? self-tim ed write cy cle (including auto-erase) ? page-write buffer for up to 16 by tes ? 2 m s ty pical write cy cle tim e for page-write ? hardware write protect for entire m e m o ry ? can be operated as a serial rom ? factory program m i ng (qtp) available ? esd protection > 4,000v ? 1,000,000 erase/write cy cles guaranteed* ? data retention > 200 y ears ? 8-pin dip ? tem p erature range -40 to +85 o c pin connection 1 8 2 7 3 6 4 5 a0 vc c a1 wp a2 scl vss s da 1
KK24LC04B/08b figure 1. representative block diagram electrical characteristics maxim u m ratings* p a r a m e t e r v a l u e v cc 7.0 v all inputs and outputs w.r.t.vss -0.3v to vcc + 1.0v storage tem p erature -65 o c to +150 o c am bient tem p . with power applied -40 to +85 o c soldering tem p erature of leads (10 seconds) +300 o c esd protection on all pins > 4 kv dc characteristics vcc = +2.5v to +5.5v com m e rcial: tam b = -40to +85 param e t e r s y m b ol m i n m a x units m o d e wp, scl and sda pins: high level input voltage low level input voltage hy steresis of schm itt trigger inputs low level output voltage v lh v il v hys v ol 0.7v cc - 0.05v cc - - 0.3v cc - 0.40 v v v v note 1 i ol = 3.0m a, v cc = 2.5v input leakage current i li - 1 0 1 0 a v ln =0.1v to v cc output leakage current i lo - 1 0 1 0 a v out =0.1v to v cc pin capacitance (all inputs/outputs) c in c out - 1 0 pf v cc = 5.0v (not e 1) tam b =25 o c, fclk =1 mhz operating current i cc writ e i cc read - - 3 1 ma ma v cc = 5.5v sc l = 400khz standby current i ccs - - 30 100 a a sda=scl=v cc =3.0v, sda=scl=v cc =5.5v 2
figure 2. bus tim ing start/stop ac characteristics standard mode vcc = 4.5 - 5.5v fas t mode parameter symbol min m a x m i n m a x units remarks clock frequency f clk - 1 0 0 - 4 0 0 k h z clock high tim e t high 4 0 0 0 - 6 0 0 - n s clock low tim e t low 4 7 0 0 - 1 3 0 0 - n s sda and scl rise tim e t r - 1 0 0 0 - 3 0 0 n s n o t e 2 sda and scl fall tim e t f - 3 0 0 - 3 0 0 n s n o t e 2 start condition hold tim e t hd: sta 4 0 0 0 - 6 0 0 - n s after this period the first clock pulse is generated start condition setup tim e t su:sta 4 7 0 0 - 6 0 0 - n s only relevant for repeated s t art condition data input hold tim e t hd: dat 0 - 0 - n s data input setup tim e t su: dat 2 5 0 - 1 0 0 - n s stop condition setup tim e t su:sto 4 0 0 0 - 6 0 0 - n s output valid from clock t aa - 3 5 0 0 - 9 0 0 n s n o t e 1 bus free tim e t buf 4 7 0 0 - 1 3 0 0 - n s time the bus must be free before a new tra n smission c a n sta r t output fall tim e from v ih mi n to v il ma x t of - 2 5 0 2 0 + 0 . 1 c b 2 5 0 n s note2, c b 100pf input filter spike suppres-sion (sda & scl pins) t sp - 5 0 - 5 0 n s note 3 write cy cle tim e t wr - 1 0 - 1 0 m s by te or page m ode note 1: as a transm itter, the device m u st provide an internal m i nim u m delay tim e to bridge the undefined region (m inim um 300 ns) of the falling edge of sc l to avoid unintended ge neration of start or stop conditions. note 2: not 100% tested. c b = total capacitance of one bus line in pf. note 3: the com b ined t sp and v hys specifications are due to new schm itt trigger inputs which provide im proved noise and spike suppression. this elim inates the need for a ti specification for standard operation. 3 KK24LC04B/08b
figure 3. bus tim ing data functional description the KK24LC04B/08b supports a bidirectional two wire bus and data transmission protocol. a device that sends data onto the bus is defined as transm itter, and a device receiving data as receiver. the bus has to be controlled by a m a ster device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions, while the KK24LC04B/08b works as slave. both, m a ster and slave can operate as transm itter or receiver but the m a ster device determ ines which m ode is activated. bus characteristics the following bus protocol has been defined: data transf er m a y be initiated only when the bus is not busy. during data transfer, the data line m u st rem a in stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (see figure 4). bus not busy (a) both data and clock lines rem a in high. start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determ ines a start condition. all com m a nds m u st be preceded by a start condition. stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determ ines a stop condition. all operations m u st be ended with a stop condition. data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line m u st be changed during the lo w period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and term inated with a stop condition. the num ber of the data bytes transferred between the start and stop conditions is determ ined by the m a ster device and is theoretically unlim ited, although only the last sixteen will be stored when doing a write operation. w h en an overwrite does occu r it will replace data in a first in first out fashion. 4 KK24LC04B/08b
acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the m a ster device m u st generate an ex tra clock pulse which is associated with this acknowledge bit. note: the kk 24lc04b/08b does not generate any acknowledge bits if an internal programming cycle is in progress the device that acknowledges, has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable lo w during the high period of the acknowledge related clock pulse. of course, setup and hold tim es m u st be taken into account. a m a ster m u st signal an end of data to the slave by not generating an acknow ledge bit on the last byte that has been clocked out of the slave. in this case, the slave m u st leave the data line high to enable the m a ster to generate the stop condition. figure 4. data transfer sequence on the serial bus bus characteristics device addressing and operation a control byte is the first byte received following the start condition from the m a ster device. the control byte consists of a four bit control code, for the KK24LC04B/08b this is set as 1010 binary for read and write operations. the next three bits of the control byte are the block select bits (b2, b1, bo). b2 is a don' t care for both the kk 24lc04b and kk 24lc08b; b1 is a don't care for the kk 24lc04b. they are used by the master device to se lect which of the two or four 256 word blocks of m e m o ry are to be accessed. these bits are in effect the m o st significant bits of the word address. the last bit of the control byte defines the operation to be perform e d. w h en set to one a read operation is selected, when set to zero a write operation is selected. following the start condition, the kk 24lc04b/08b monitors the sda bus checki ng the device type identifier being transmitted, upon a 1010 code the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the KK24LC04B/ 08b will select a read or write operation. operation control code block select r/w r e a d 1 0 1 0 b l o c k a d d r e s s 1 w r i t e 1 0 1 0 b l o c k a d d r e s s 0 5 KK24LC04B/08b
KK24LC04B/08b figure 5. control byte allocation write operation byte write following the start condition from the m a ster, the device code (4 bits), the block address (3 bits), and the r/w bit which is a logic low is placed onto the bus by the m a ster transm itter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore the next byte transm itted by the m a ster is the word address and will be written into the address pointer of the kk 24lc04b/08b. after receiving another acknowledge signal from the kk24l c04b/08b the master device will transmit the data word to be written into the addressed m e m o ry location. the KK24LC04B/08b acknowledges again and the m a ster generates a stop condition. this initiates the internal write cycle, and during this tim e the KK24LC04B/08b will not generate acknowledge signals (see figure 6). page write the write control byte, word address and the f i rs t data byte are transm itted to the KK24LC04B/08b in the sam e way as in a byte write. but instead of generating a stop condition the m a ster transm its up to sixteen data bytes to the KK24LC04B/08b wh ich are temporarily stored in the on-chip page buffer and will be written into the m e m o ry after the m a ster has transm itted a stop condition. after the receipt of each word, the four lower order addr ess pointer bits are internally increm ented by one. the higher order seven bits of the word address rem a ins constant. if the m a ster should transm it m o re than sixteen words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwr itten. as with the byte write operation, once the stop condition is received an internal write cycle will begin (see figure 8). figure 6. byte w r ite 6
acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determ ine when the cycle is com p lete (this feature can be used to m a xim i ze bus throughput). once the stop condition for a write com m a nd has been issued f r om the m a ster, the device initiates the internally tim ed write cycle, ack polling can be initiated im m e diately. this involves the m a ster sending a start condition followed by the control byte for a write com m a nd (r/w =0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is com p lete, then the device will return the ack and the m a ster can then proceed with the next read or write com m a nd. see figure 7 for flow diagram . write protection the KK24LC04B/08b can be used as a serial rom when the w p pin is connected to vcc. program m i ng will be inhibited and the entire m e m o ry will be write-protected. read operation read operations are initiated in the sam e way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read, and sequential read. figure 7. acknowledge polling flow current address read the KK24LC04B/08b contains an address counter that maintains the address of the last word accessed, internally increm ented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current addr ess read operation would access data from address n + 1. upon receipt of the slave address with r/ w bit set to one, the KK24LC04B/08b issues an acknowledge and transm its the eight bit data word. the m a ster will not acknowledge the transfer but does generate a stop condition and the kk24l c04/08 discontinues transmission (see figure 9). random read random read operations allow the m a ster to access any m e m o ry location in a random m a nner. to perform this type of read operation, first the word address m u st be set. this is done by sending the word address to the KK24LC04B/08b as part of a write operation. after the word address is sent, the m a ster generates a start condition followi ng the acknowledge. this term inates the write operation, but not before the internal address pointer is set. then the m a ster issues the control byte again but with the r/w bit set to a one. the kk 24lc04b/08b will then i ssue an acknowledge and transm its the eight bit data word. the m a ster w ill not acknowledge the transfer but does generate a stop condition and the kk 24lc04b/08b discontinues transmission (see figure 10). 7 KK24LC04B/08b
figure 8. page w r ite figure 9. current address read figure 10. random read sequential read sequential reads are initiated in the sam e way as a random read except that after the kk 24lc04b/08b transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the kk 24lc04b/08b to transmit the next sequentially addressed 8 bit word (see figure 11). to provide sequential reads the KK24LC04B/08b c ontains an internal address pointer which is increm ented by one at the com p letion of each operation. this address pointer allows the entire m e m o ry contents to be serially read during one operation. noise protection the kk 24lc04b/08b employs a vcc threshold det ector circuit which disables the internal erase/write logic if the vcc is below 1,5 volts at nom inal conditions. the scl and sda inputs have schm itt trigger and f ilter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. 8 KK24LC04B/08b
figure 11. sequential read pin descriptions spa serial address/data input/output this is a bidirectional pin used to transfer addresses and data into and data out of the device. it is an open drain term inal, therefore the sda bus requires a puliup resistor to vcc (typical 10k ? for 100 khz, 1 k ? for 400 khz ). for norm a l data transf er sda is allowed to ch ange only during scl low. changes during scl high are reserved for indicating the start and stop conditions. scl serial clock this input is used to synchronize the data transfer from and to the device. wp this pin m u st be connected to either vss or vcc. if tied to vss, norm a l m e m o ry operation is enabled (read/write the entire m e m o ry). if tied to vcc, w r ite operations are inhibited. the entire m e m o ry will be write-protected. read operations are not affected. this feature allows the user to use the kk 24lc04b/08b as a serial rom when wp is enabled (tied to vcc). a0,a1,a2 these pins are not used by the KK24LC04B/08b. they may be left floating or tied to either vss or vcc. 9 KK24LC04B/08b
n s u f f i x p l as t i c di p ( m s ? 00 1b a ) sy m b o l m i n m a x a 8. 51 10. 16 b 6. 1 7 . 1 1 c 5. 33 d 0. 36 0. 56 f 1. 14 1. 78 g h j 0 10 k 2. 92 3. 81 no t e s : l 7. 62 8. 26 1. d i m e n s i o n s ?a ?, ?b ? d o n o t i n cl u d e m o l d f l as h o r p r o t r u s i o n s . m 0. 2 0 . 3 6 m a x i m u m m o l d f l a s h o r p r o t r u s i o n s 0. 25 m m ( 0 . 010) p e r s i d e . n 0. 38 d su f f i x so i c (m s - 0 1 2 a a) sy m b o l m i n m a x a 4. 8 5 b 3. 8 4 c 1. 35 1. 75 d 0. 33 0. 51 f 0. 4 1 . 2 7 g h j 0 8 no t e s : k 0. 1 0 . 2 5 1. d i m e n s i o ns a a n d b d o no t i n c l ud e m o l d f l a s h o r p r ot r u s i on . m 0. 19 0. 25 2. m a x i m u m m o l d f l a s h o r p r o t r u s i o n 0. 15 m m ( 0 . 006) p e r s i d e p 5. 8 6 . 2 fo r a ; fo r b ? 0. 25 m m ( 0 . 010) p e r s i d e . r 0. 25 0. 5 1. 27 5. 72 d i me n s i o n , mm d i me n s i o n , mm 2. 54 7. 62 a b h c k c m j f m p g d r x 4 5 se a t i n g pl a n e 0 . 25 (0 . 0 10 ) m t -t - 1 8 4 5 l h m j a b f g d se a t i n g pl a n e n k 0 . 2 5 ( 0 .01 0 ) m t -t - c 1 8 4 5 10 KK24LC04B/08b
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